This invention relates to an ATM (asynchronous transfer mode) cell multiplexing device for multiplexing ATM cells.
An ATM cell multiplexing device of the type described, generally comprises first through N-th input lines supplied with first through N-th input signals, each having a predetermined bit rate V to represent successive ATM cells classifiable into valid and invalid cells, where N represents an integer greater than one. The invalid cells will be called empty or idle cells in the art. The ATM cell multiplexing device further comprises at least one output line and a processing section connected to the first through the N-th input lines and to the output line. The processing section processes the first through the N-th input signals into a time division multiplexed output signal having the predetermined bit rate V. The processing section delivers the time division multiplexed output signal to the output line. Such an ATM cell multiplexing device is described in a paper contributed by Hiroshi SUZUKI et al to IEEE International Conference on Communications, CH2655-9 (1989), pages 0099-0103, under the title of "Output-buffer Switch Architecture for Asynchronous Transfer Mode".
As will later be described in connection with a conventional ATM cell multiplexing device, the processing section comprises a time division multiplexing section connected to the first through the N-th input lines for time division multiplexing the first through the N-th input signals into a time division multiplexed signal having a preselected bit rate V.times.N and comprising first through N-th multiplexed cell or components. The first through the N-th multiplexed cells are derived from the first through the N-th input signals, respectively.
A first-in first-out (FIFO) memory is connected to the time division multiplexing section. A controller is connected to the time division multiplexing section and to the first-in first-out memory for controlling the first-in first-out memory to successively write the valid cells of the first through the N-th multiplexed cells in the first-in first-out memory as written cells at a writing rate or speed equal to 2.times.V.times.N and to read the written cells out of the first-in first-out memory in a first-in first-out order as a read-out signal at a reading rate or speed equal to 2.times.V.times.N. Inasmuch as the writing operation is not carried out simultaneously with the reading operation for the first-in first-out memory using a single port RAM, each of the writing and the reading rates is inevitably made to become equal to twice the preselected bit rate V.times.N to carry out the reading and the writing operation in a time division fashion.
A converter is connected to the first-in first-out memory and to the output line. The converter converts the read-out signal into the time division multiplexed output signal of the predetermined bit rate V to deliver the time division multiplexed output signal to the output line.
In order to realize the ATM cell multiplexing device having a large scale and a high speed, it is required to reduce an accessing speed (namely, the writing and the reading rates or speeds) to the first-in first-out memory.